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Cu(In, Ga)Se2 solar cells are the representative of high efficient thin-film solar cell with energy conversion efficiency of over 22%. However, nowadays, top electrodes of solar cells gradually become the performance limitation for optimized devices. The Al-doped ZnO thin film is widely used as a transparent top electrode in Cu(In, Ga)Se2, but there are still some techniques and electrical property...
Current 2D planar NAND has its limitation for expanding capacity due to the performance and reliability intrinsic characterization will be impacted as device scaling below the 20nm technology node. Such as write bits error, data retention and read disturb, etc. Continued scaling increases the effect of cell-to-cell interference, which widens the program state width. 3D vertical stacking memory cells...
A novel three-dimensional (3D) NAND structure containing both vertical gate (VG) framework and gate-all-around (GAA) cell structure is innovated and demonstrated. It is fabricated on alternating layers of silicon dioxide (OX) and polysilicon (PL) by using 43nm technology. To our knowledge, one of the major advantages of the novel structure is the smaller cell unit footprint than vertical channel (VC)...
Pattern dependent charging effect is explored in this study. Due to increased film thickness in 3D NAND structure, a derivative problem-the plasma-induced charging damage is enhanced during high aspect ratio (HAR) etching. In this paper, several effective methods are demonstrated to alleviate the impact of profile distortion due to charging effect while etching high aspect ratio (>14) trenches.
The Web consists of a huge number of structured data in the form of tables, which makes automatically integrating information from those tables of interest to ordinary users possible. A key problem of web table integration is the discovery of correspondences between web table columns. Most of traditional schema matching techniques can't work well because of the lack of schema information and the small...
This paper presents a case study on a process excursion where a subtle defect spray with twelve pairs of defects aggregated flow pattern on the front side of the wafer. The defect of interest is molten tungsten (W) balls which are generated in a dielectric etch chamber caused by plasma arcing between one part of the etch chamber and the dissimilar W film remaining on the wafer bevel. Observations...
The study focus on the process of metal electroplating on copper substrate to assemble LED chips and molding PET-copper foil to implement a flexible module with LED chips. The process can be divided into two parts,-assembling process and molding process. The LEDs are integrated on copper foil which can deal with the heat dissipation problem effectively. The metal electroplating on copper circuitry...
The study focus on the process of metal electroplating on copper substrate to assemble LED chips and molding PET-copper foil to implement a flexible module with LED chips. The process can be divided into two parts,-assembling process and molding process. The LEDs are integrated on copper foil which can deal with the heat dissipation problem effectively. The metal electroplating on copper circuitry...
This paper proposes a novel algorithm for optimization of automatic stereoscopic camera parameters based on 3D cinematography principles that control disparity range, as well as the stereo window violation (SWV) and temporal continuity of the disparity (TCD). By following these principles, the user can input the arbitrary range of the disparity and assign the ratios of the disparity adjusting function...
The topic of this paper is to identify tungsten plug corrosion issue at the interface of barrier metal and W bulk in W-CMP process. Two types of nucleation layers in W-CVD deposition process - SiH4 and B2H6 based were studied. The B2H6 based nucleation W will induce W corrosion. However, SiH4 based nucleation W does not have the issue. The static etch rate, electrochemical properties and removal rate...
This investigation employs an optimized method to alleviate defects occurring at BF2+ implanted source/drain areas, some white spots defects found at scribes lines after BPSG (boron and phosphorus doped silicon glass) anneal. The results of physical failure analysis indicate the white spot defects are relative to outgassed fluorine that can't be released out during BPSG thermal annealing. Various...
This paper presents a unique gate structure for reducing shorts between word lines on charge-trapping flash cell memory. In the early stage of developing sub-45 nm half-pitch word line by a self-aligned double patterning (SADP) technology, the cell array suffered from abnormal intrinsic word line-to-word line shorts, ca. 96.3% of the bridge rate on the 72 Mb cell memory, due to the formation of polysilicon...
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