The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A novel Built-in Self-Test (BIST) approach to test the configurable Input/Output buffers in Xilinx Virtex series SOCs using Hard Macro has been proposed in this paper. The proposed approach can completely detects single and multiple stuck-at gate-level faults as well as associated routing resources in I/O buffers. The proposed BIST architecture has been implemented and verified on Xilinx Virtex series...
This paper presents a built-in self-test (BIST) approach to test embedded memory blocks in configurable system-on-chips (SoCs). The idea of this paper is to develop BIST architecture and BIST configurations for testing embedded memory blocks in Xilinx Virtexl-4 series SoCs by using an embedded FPGA core. The proposed approach tests RAMs operating in all of different sizes both in single-port and dual-...
This paper presents a built-in self-test (BIST) approach for testing configurable logic and memory resources in Xilinx Virtex FPGAs using hard-macro. The resources under test include the configurable logic blocks (CLBs) and block random access memories (BRAMs) in all of their modes of operation. The proposed approach completely detects and diagnoses single and multiple stuck-at gate-level faults of...
This paper explores an new Built-In Self-Test (BIST) approach to test the configurable logic blocks (CLBs) of Xilinx Virtex FPGAs using Hard Macro. The proposed approach completely detects and diagnoses single and multiple stuck-at gate-level faults as well as associated signal lines in the CLBs, while significantly reducing the Outputs needed to be compared by ORAs. Only 24 total test configurations...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.