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In this paper, we report a Vt tuning technique by dipole-engineering dopant incorporation in the FinFET metal gate stack. Remote interfacial layer scavenging induced by the metal gate dopants has an added advantage of improving the CET, without impacting short channel behavior. Using Al as the dipole-inducing dopant in a FinFET gate stack, a 170mV of positive Vt shift with 0.8Å CETinv reduction was...
We report significant improvements in the high-k/In0.53Ga0.47As interface quality by controlling atomic layer deposition (ALD) oxidizer chemistry. A step-by-step correlation between electrical data and chemical reactions at the high-k/InGaAs interface has been established using synchrotron photoemission. AsOx, GaOx, and In2O3 formed during unintentional ALD surface oxidation and the increase of As-As...
Floating gate (FG) devices using barrier-engineered (BE) tunneling dielectric have been studied both theoretically and experimentally. Through WKB modeling the tunneling efficiency of various multi-layer tunneling barriers can be well predicted. Experimental results for FG devices with oxide-nitride-oxide (ONO) U-shaped barrier are examined to validate our model. Furthermore, a large-density array...
A comprehensive materials set has been fabricated and characterized to address the challenging issues in both gate first and gate last HK/MG CMOS. Specifically, metal gate thermal budget and channel composition are shown to be effective methods to engineer pMetal effective work function for gate last and gate first, respectively. Low temperature processing has resulted in low nMOS Vfb and high pMOS...
Although III-V semiconductors have intrinsically higher electron mobility compared to Si, a high-quality gate stack with low Dit is still required to realize III-V surface channel MOSFETs. Recently, significant effort has been focused on improving high-k/III-V interfaces using different interfacial passivation layers (IPL) and surface passivation techniques. These include MBE deposition of Ga2O3(Gd...
A reliability study of high-k/metal gate stack transistors with a sub-nanometer equivalent oxide thickness (EOT) and engineered interfacial layer (IL) having a k value higher than that of conventional SiO2 thin film is reported. The mobility reduction in these ldquozerordquo SiOx IL devices exhibits a consistent trend of a positive charge buildup and increased interface state density associated with...
This paper reports on a scalable and simple gate-first integration option for manufacturing the high-k/metal gate CMOS transistors targeting sub-32 nm LSTP applications: Vt < plusmn 0.45 V (at Lg = 60 nm) at EOT les 1.4 nm, with 105 times Jg reduction compared to SiO2. This scheme integrates several simplifications and improvements for the first time: single metal gate material, single channel...
Gate first 0.59 nm EOT HfOx/metal gate stacks for 16 nm node application are demonstrated for the first time. By controlling O during HfOx deposition, ldquozerordquo low-k SiOx interface (ZIL) forms despite a 1020degC activation anneal. This 0.59 nm EOT is a 30% improvement over a state of the art 32 nm HK/MG technology. We compare and demonstrate for the first time the improved scalability of ZIL...
This letter addresses mechanisms responsible for a high gate leakage current (Jg) and a thick interfacial layer in the surface channel SiGe pFET enabling transistor fabrication with sub-1-nm equivalent-oxide-thickness (EOT) high-k /metal gate stack. The primary mechanism limiting EOT scaling is Ge-enhanced Si oxidation resulting in a thick (1.4-nm) SiOx interface layer. A secondary mechanism, i.e...
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