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In this paper, we propose and investigate two novel applications of absorbing materials to suppress high-frequency couplings in high-speed interconnects. In the first application, absorbing materials are added to connector housing to reduce the noises caused by crosstalk and resonances. In the second application, a low-emission inductor is proposed by applying absorbing materials surrounding the body...
As integrated circuit (IC) chips keep growing in size, I/O data rates and complexity, electrical margin left on printed circuit board (PCB) gets smaller. Mid-loss or even low-loss material may be needed in more cases to meet high speed (HS) signal routing length requests, which leads to cost-adder on PCB. This submission introduces analysis flow as well as practical methods targeting reducing PCB...
In this paper, the signal integrity (SI) simulation and computer system electrical design flow is discussed. Traditionally, the SI analyses lead to a set of physical design rules that the printed-circuit board (PCB) and integrated circuit (IC) package designers rigorously follow in the layout to ensure the signaling performance meets the requirements. Such practice makes the signaling requirements...
Due to non-LTI behaviour of re-driver, simulation methodology and model format are still working in progress for continuous improvement on accuracy and efficiency to perform statistical analysis such as BER for high-speed serial IO links. In this paper, a measurement based methodology is proposed and introduced to provide a flow and methodology to evaluate re-driver link performance. The methodology...
In this paper, a fast signal integrity methodology using pseudo eye is introduced to characterize printed circuit board (PCB) channels. The pseudo eye and pseudo ratio are proposed as performance indicators of the channel. This methodology can be applied to not only the solution space check during the pre-layout design phase but also layout quality check before PCB manufacture. For pre-layout analysis,...
The board-level signal integrity, a new methodology to indicate the performance quality of a PCB channel, is introduced in this paper. Instead of the eye height and the eye width, the pseudo eye and amplitude ratio are defined as performance indicators of a PCB channel. The two applications of board-level signal integrity methodology are also given.
Traditionally, Intel supports ODM/OEM (original design manufacturer / original equipment manufacturer) IO bus designs via PDG (platform design guide). If IO bus design is out of PDG guidelines (OOG), usually Intel cannot support it. However, Intel is experiencing overwhelming customer requests for OOG support since more and more customers are designing products OOG for cost vs. performance tradeoff...
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