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A new charge pump circuit with a clock that shows an increased clock voltage as its stage is increased is proposed in the paper. The charge pump circuit utilizes the cross-connected NMOS, voltage doubler, as a pumping stage. Each stage of the voltage-doubler provides a pair of complementary clock voltages. The clock voltage also increases as the stage of voltage doubler is increased. It shows that...
A high efficiency charge pump circuit which is realized by multi-staged high-voltage clock (HVC) generator is presented. The ten-staged HVC charge pump circuit could pump the voltage up to 21.35 V at a supply voltage of 2 V in 0.35 mum CMOS process. It also shows that the clock voltage increased linearly as the stages of the high-voltage clock generator was increased. No saturation tendency of the...
A high efficiency new charge pump circuit was proposed in the paper. A clock scheme which designed by multi-staged voltage doubler was used in the Dickson charge pump structure. Very high voltage could be reached through the pumping of the new charge pump circuit. By the simulation of HSpice under 0.35 mum process, 2 V supply voltage and clock voltage. It showed a voltage up to 40.37 V was obtained...
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