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This paper presents a wireline communication receiver with merged continuous-time linear equalizer (CTLE) and decision feedback equalizer (DFE) summer circuit. The merged circuit removes the traditional CTLE and merge it into the following DFE summer to builds linear equalization so as to significantly reduce the receiver power consumption. Analysis for the conventional equalizer and proposed circuit...
This paper presents an energy-efficient high-speed hybrid dynamic comparator with reduced delay in 40-nm CMOS process. The first dynamic amplifying stage uses PMOS input to reduce the common-mode voltage, thus the required minimum supply voltage, while enhancing the positive feedback to reduce the discharge time in a low-power manner. The second quasi-dynamic latching stage uses NMOS input to gain...
This paper presents a 20-Gb/s half rate 4:1 multiplexer (MUX) with multiphase clock (MPC) architecture in 40-nm CMOS technology. The MPC architecture employs quarter-rate four-phase clock generated by true phase single clock divider, which omits the phase adjuster and delay-matching buffers and thus reduces power consumption. Meanwhile, The MUX is implemented by purely digital circuits contributing...
We present a direct sampling full-band capture receiver for cable and digital TV applications. It consists of a 28nm CMOS ADC-based direct sampling receiver and a 0.18um BiCMOS LNA. It is capable of receiving 158 channels from 48MHz to 1000MHz simultaneously, achieving up to 10Gb/s data throughput, while exceeding DOCSIS requirements. The CMOS receiver occupies 1mm2 area while consuming 300mW. The...
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