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A figure of merit (FOM) for a CMOS system on chip (SoC) is proposed to correctly assess different CMOS SoCs in the near-threshold voltage ($V_{{\rm {th}}})$ region, where the supply voltage ($V_{{\rm {DD}}})$ is slightly higher than $V_{{\rm {th}}}$ . When $V_{{\rm {DD}}}$ is scaled down to near $V_{{\rm {th}}}$ , the drain current becomes greatly sensitive to $V_{{\rm {DD}}}$ or $V_{{\rm {th}}}$ ...
Despite improved device performance over traditional Poly-SiON technology, high-K metal gate flow introduces additional device variations not previously seen in Poly-SiON process, especially impacting large dimensional (WxL) devices for matching critical applications. For the first time, we report a comprehensive analysis of device variations introduced from metal gate process, GDIM and GGIM, and...
We present, for the first time, a holistic system-circuit-transistor co-optimization method, named “Critical Path Aware (CPA) transistor optimization”, through which we demonstrate power reduction of more than 20% in a state-of-the-art SoC design. In this method, we simplify and optimize all paths (critical and non-critical) to guide device design point for maximum power-performance benefit. We introduce...
As technology scales down, an increasing number of transistors can be integrated into a single chip but process variation becomes more serious. SRAM is one of the key components in a SoC and it occupies a large portion of the SoC. Thus, the SRAM bitcell is typically designed using very small transistors for high integration, which limits the minimum operating voltage (VCCmin) of the SoC because of...
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