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The integration of a differential antenna in mainstream 65 nm CMOS was investigated. A 60 GHz prototype integrated circuit (IC) was developed, including a seal-ring and on-chip calibration structures. Measured results show excellent impedance matching properties over a 10 GHz bandwidth and a moderate antenna gain of −1.5 dBi. However, this is still a significant improvement as compared to state-of-the-art...
Hf 1−x Si x O y is an attractive candidate material for high-k dielectrics. We report in this work the deposition of ultra-thin Hf 1−x Si x O y films (0.1≤x≥0.6) on silicon substrate at 450°C by UV-photo-induced chemical vapour deposition (UV-CVD) using 222nm excimer lamps. Silicon(IV) and hafnium(IV) organic compounds were used as the precursors. Films...
ESD protection strategies utilized in RF circuit applications in CMOS and BiCMOS technologies are investigated and the results are presented in this paper. The conventional approach using diodes with power clamp is compared with novel approaches such as plug-and-play passive elements and full or partial circuit-ESD co-design. The trade-offs are discussed from both RF and ESD point of views. Common...
An advanced low power, strained channel, dual poly CMOS 65nm technology with enhanced transistor performance is presented. At 1V and off current of 100nA/mum, transistors have record currents of 1.21mA/mum and 0.71mA/mum for NMOS and PMOS respectively. This industry leading 65nm technology is currently in high volume manufacturing
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