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The main purpose of this work is to investigate the characteristics of a 180nm CMOS technology with high voltage (HV) option in view of the fabrication of a dual-tier, low material budget sensor for charged particle detection. For this purpose, an array of avalanche pixels has been designed. The array includes sensors with a pitch of 50μmx100μm, different sizes (20μmx20μm, 30μmx30μm and 40μmx36μm)...
This work describes the development of a novel position sensitive charged particle detector suitable for nuclear physics applications, in the field of High Energy Physics experiments and emerging medical applications such as hadrontherapy and Proton Computed Tomography (pCT). The “3D Silicon Coincidence Avalanche Detector” (3D-SiCAD) pixel consists of a pair of 3D vertically aligned Geiger-mode avalanche...
Optical crosstalk is one of the main factors limiting the performance of Single-Photon Avalanche Diode (SPAD) arrays and Silicon Photomultipliers (SiPMs). In this paper, a set of crosstalk measurements on a CMOS SPAD pixel array with 50µm × 75µm pitch and 51.6% Fill Factor, designed for direct particle detection, is reported. Measurements were performed on dies with different thickness: 280µm, 50µm...
In this paper, a novel SPAD architecture implemented in Silicon-On-Insulator (SOI) CMOS technology is proposed. Thanks to its intrinsic 3D structure, the proposed solution is expected to allow very small pixels while enabling a very high fill factor. Furthermore, the pixel read-out electronics as well as the whole detector electronics can benefit of the well-known advantages brought by SOI technology...
In this paper, a time-integration based passive quenching — active recharge circuit for Geiger-mode avalanche diodes has been proposed with the aim of minimizing the avalanche charge and providing a hold-off time tunable within wide range. These are indeed important features to be taken into account in the design of the avalanche diode quenching — reset electronics. Furthermore a hold-off time tunable...
A 130 nm CMOS evaluation chip intended to read Silicon strip detectors has been designed and successfully tested. Optimized for a detector capacitance of 10 pF, it includes four channels of a full signal processing chain, including low-noise charge integration and pulse shaping, a 16 deep-analog sampler triggered on an analogue sum of adjacent inputs, and a parallel 10-bit analog to digital conversion...
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