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This paper develops a new approach to design static threshold gates with hysteresis, based on integrating each pair of pull-up and pull-down transistor networks into one composite transistor network. The new static gates are then compared to the original ones in terms of delay, area, and energy consumption. In order to compare the new gate style with the original one at the circuit level, a delay-insensitive...
This paper develops a new approach to design static threshold gates with hysteresis, based on integrating each pair of pull-up and pull-down transistor networks into one composite transistor network. The new static gates are then compared to the original ones in terms of delay, area, and energy consumption. In order to compare the new gate style with the original one at the circuit level, a delay-insensitive...
Various CMOS implementations of asynchronous NULL Convention Logic (NCL) gates have been compared in terms of area, speed, energy, power, supply voltage, and noise. Additionally, a new approach to design semi-static NCL gates has been introduced. Each gate type is used to realize a delay-insensitive 4×4 NCL multiplier and the simulation results are compared. It is shown that different realizations...
In the literature, quasi-delay-insensitive (QDI) asynchronous circuits utilizing Pre-Charge Half Buffers (PCHB) are based on either dynamic or semi-static implementations. In this paper, a static implementation of PCHB is presented, and compared to previous PCHB architectures and static NULL Convention Logic (NCL), using a full adder design. Transistor level simulation shows that the static PCHB architecture...
This paper demonstrates the performance, area and supply voltage scaling advantages of a Differential Cascode Voltage-Switch Logic (DCVSL)-like design over previous methods for designing C-elements. The DCVSL-like method is then applied to the design of arbitrary NULL Convention Logic (NCL) gates, which have hysteresis state-holding capability.
This paper develops an ultra-low power design methodology for bit-wise pipelined asynchronous circuits, called bit-wise MTNCL, which combines multi-threshold CMOS (MTCMOS) with bit-wise pipelined NULL Convention Logic (NCL) systems. Compared to original NCL circuits implemented with all low-Vt and high-Vt transistors, respectively, it provides the leakage power advantages of the all high-Vt NCL implementation...
We report a novel tunneling field effect transistor (TFET) fabricated with a high-k/metal gate stack and using nickel silicide to create a special field-enhancing geometry and a high dopant density by dopant segregation. It produces steep subthreshold swing (SS) of 46 mV/dec and high ION/IOFF ratio (~108) and the experiment was successfully repeated after two months. Its superior operation is explained...
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