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Standby power is one of the most critical issues in low power chip applications. In this paper, we have investigated the effects of body bias and source bias in 65 nm technology through simulations on SRAM standby current (Isb). The simulation results show a 8X reduction in cell Isb at 125degC FF process corner with a 1.0 V NMOS body bias. This has been experimentally verified on a 16 Mb SRAM testchip...
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