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We have realized a practical wide band gap in bilayer graphene. The gap was induced by an electric field applied by dual-gate sandwiching the bilayer graphene. A self-assembled gate insulator enabled us to apply a large electric field which enhanced the band gap. The wide band gap allowed for operation of a logic gate composed of bilayer graphene transistors. These results predict that graphene electronics...
We demonstrate a photonic logic gate for RZ-PolSK signals based on bidirectional FWM in HNLF. Multi-function, such as XOR, ̄AB, ̄AB, XNOR, AND, NOR, half-subtracter, half-adder, comparator and decoder, are simultaneously implemented.
150 mm Silicon-on-polycrystalline-Silicon Carbide (poly-SiC) hybrid substrates, without intermediate oxide layers have been realized by hydrophilic wafer bonding of SOI- and poly-SiC wafers. A novel rapid thermal treatment step has been introduced before furnace annealing to avoid bubble formation, cracks and breakage. The final substrates are shown to be stress-free. Electrical and thermal characterization...
This paper presents a power flow control method for contactless power transfer systems. The proposed method is to control the magnitude of the primary track current based on the concept of energy injection and regeneration. The stored energy and resonant current is controlled to vary on the primary side. As a result, the induced current on the secondary side varies. For such a reason, the power flow...
A high performance CMOS HK/MG sub 1nm EOT solution is demonstrated. The drive currents at Ioff = 100 nA/μm with VDD = 1 V are 1.25 mA/μm and 0.56 mA/μm for n and pMOS respectively without strain boost. Through a novel process integration design, PMOS EWF roll-off and NBTI problems with EOT scaling are overcome until sub 1nm EOT region. The PMOS -0.25V Vt @1um Lg and NBTI 10 years life time @0.7V overdrive...
An all-optical logic unit based on both FWM and XGM arising in a single SOA is proposed. Dual-channel logic AND, NOR, and XNOR gates for CSRZ-OOK signals could be simultaneously achieved without reconfiguration.
Internally-matched 4H-SiC MESFET with 4times20 mm of the total gate width was demonstrated. The SiC MESFET structure consists of a channel layer with doping concentration of 2.3times1017 cm-3 and a cap layer with doping concentration of 1.5times1019 cm-3. A lightly p-doped buffer layer was employed between the substrate and the channel layer. Dry etching and high-temperature oxidation were employed...
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