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We have demonstrated 1200V and 3300V planar 4H-SiC MOSFET technology at our 6-inch foundry. 1200V MOSFETs demonstrate good avalanche ruggedness under single-and one million (1,000,000) repetitive unclamped inductive switching (UIS) pulse tests. 1200V MOSFETs can pass one hundred (100) 10 microsecond short-circuit events at 600V bus voltage, while 3300V MOSFETs can pass 5 microsecond short-circuit...
Large area 6.5 kV normally-off JFETs and JBS diodes have been developed for high DC-link voltage applications. The basic performance characteristics are examined along with the switching behavior using double pulse testing at 3 kV, 11A with an inductive load. In addition, a performance comparison between the single 6.5 kV JFET and a 6.0 kV super-cascode approach, built from stacking five normally-on...
InGaAs gate-all-around (GAA) MOSFETs with implanted source and drain (S/D) structure have been demonstrated which offer large drive currents and excellent immunity to short channel effects down to deep sub-100 nm channel length [1–2]. In this work, we fabricate n++ raised S/D InGaAs GAA MOSFETs with 10nm or 20nm thick nanowires and 200nm channel length. Maximum Ion over 1 mA/μm at Vgs-Vt=1V and Vds...
We present a fully-integrated SOI CMOS 22nm technology for a diverse array of high-performance applications including server microprocessors, memory controllers and ASICs. A pre-doped substrate enables scaling of this third generation of SOI deep-trench-based embedded DRAM for a dense high-performance memory hierarchy. Dual-Embedded stressor technology including SiGe and Si:C for improved carrier...
This work presents the development of a novel bidirectional Solid State Disconnect (SSD) module based on Silicon Carbide (SiC) Junction Field Effect Transistors (JFET) capable of a fast disconnect action upon reaching a preset value of the current through the SSD. Due to the superior properties of SiC material and the low on-resistance of the normally-on SiC JFET, a very low insertion loss can be...
We report on gate-last technology for improved effective work function tuning with ∼200meV higher p-EWF at 7Å EOT, ∼2x higher fmax performance, and further options for channel stress enhancement than with gate-first by taking advantage of the intrinsic stress of metals and gate height dependence. Additional key features: 1) scavenging technique yielding UT-EOT down to ∼5Å is demonstrated in gate-last,...
In this paper, Si-MOS capacitors with HfTiO/SiON stack gate dielectric were fabricated by using Si-surface thermal passivation in NO and N2O ambients respectively and reactive co-sputtering technology. Results show that the sample pretreated in NO ambient has excellent interface properties, low gate leakage current density and high reliability. This is attributed to the formation of a SiON interlayer...
Dielectric breakdown in advanced gate stacks in state-of-the-art Si nanoelectronic devices has been one of the key front-end reliability concerns for further CMOS technology downscaling. In this paper, we present the latest findings in using physical analysis techniques such as transmission electron microscopy (TEM)/electron energy loss spectroscopy (EELS)/energy dispersive X-ray spectroscopy (EDS),...
This is a brief review of recent work on the prospective hybrid CMOS/memristor circuits. Such hybrids combine the flexibility, reliability and high functionality of the CMOS subsystem with very high density of nanoscale thin film resistance switching devices operating on different physical principles. Simulation and initial experimental results demonstrate that performance of CMOS/memristor circuits...
Reliability study of high-κ (HK) gate dielectric based transistors has become imperative for the current and future CMOS technology nodes as the industry shifts towards replacement of conventional silicon oxynitride (SiON) with hafnium-based oxides. One of the key requirements of any oxide reliability study is a quantitative assessment of the time dependent dielectric breakdown (TDDB) lifetime using...
In order to achieve aggressive scaling of the equivalent oxide thickness (EOT) and simultaneously reduce leakage currents in logic devices, silicon-based oxides (SiON / SiO2) have been replaced by physically thicker high-κ transition metal oxide thin films by many manufacturers starting from the 45 nm technology node. CMOS process compatibility, integration and reliability are the key issues to address...
The paper reports the impact of TiN metal gate composition (Ti-rich vs. N-rich) and preparation methodology (atomic layer deposition-ALD vs. physical vapor deposition -PVD) on its thermal stability with HfO2 high-K dielectric, via both physical characterization (X-ray Photoelectron Spectroscopy-XPS, High Resolution TEM combined with Electron Energy Loss Spectroscopy-EELS), and electrical characterization...
For NiSi FUSI gate transistors, switching behaviors have been observed after breakdown (BD) under certain favorable conditions. The conductive BD path can be ??switched-off?? if a reverse bias, as opposed to the stressing voltage, is applied, a condition required for observing SET and RESET conduction in switching material systems. Using the percolation model of BD of gate dielectric systems, we explain...
How can a metal-oxide-semiconductor (MOS) transistor suffer from multiple dielectric breakdowns (BD) with severe structural damages (e.g., local melting and metal migration) remain functional? Our results show that the amorphization of Si in the vicinity of the BD forms an effective p-n diode which prevents terminal short from happening when reverse-biased.
In conclusion, this paper reports a number of significant developments in III-V MOSFET devices. Retaining a subthreshold slope of 60-70 mV/decade for gate lengths down to 100 nm with an EOT of 3.4 nm shows for the first time that the flatband mode device architecture is tolerant to short channel effects. In addition, a generic silicon compatible process flow for the realization of fully self-aligned...
STEM/EELS were used to probe the localized electronic structures of the defective oxide. Our results show that the electronic structures of breakdown oxide are similar to the oxygen deficient suboxide with formation of oxygen vacancies. The understanding of the basic material properties will be helpful for the improvements of the state-of-the-art devices.
We present an improved procedure for extracting parasitic capacitance parameters and gate current parameters for MOSVAR, the industry standard MOS varactormodel. Our technique is verified against measured data from three technology nodes (180 nm, 130 nm and 65 nm), and is also used to validate the MOSVAR P-gate/P-well tunneling current sub-model.
A new integration scheme is presented to solve device and manufacturing issues for extremely thin SOI (ETSOI) technology with high-k/metal gate. Source/drain and extensions are effectively doped by an implant-free process to successfully reduce series resistance below 200 Omegaldrm. A zero-silicon-loss process is developed to eliminate loss of thin SOI layer during gate and spacer processes, enabling...
Reliability is a key performance indicator of any semiconductor device or circuit fabricated, apart from its other performance parameters such as improved current drive, clocking speed, carrier mobility, fan-in, fan-out, lower power dissipation etc. It is necessary to be able to quantitatively estimate the lifetime of a given circuit based on the accelerated life test data that is usually collected...
Using scanning transmission electron microscope with high resolution electron energy loss spectroscopy, the chemical nature of the percolation path formed in ultrathin SiON layers is studied for digital and analog breakdown (BD). Our results show that the diameter of the percolation path dilates from 30 nm to 55 nm as the gate leakage current increases from 2 muA to 40 muA. Oxygen deficiency in the...
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