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Dynamic power reduction techniques such as sequential clock-gating aim at eliminating inconsequential computation and clock-toggles of the registers. Usually sequential clock-gating opportunities are discovered manually based on certain characteristics of a design (e.g. pipelining). Since manual addition of sequential gating circuitry might change the functionality of the design, sequential equivalence...
In this paper, we present a efficient algorithm for real-time ellipse detection. Unlike Hough transform algorithm that is computationally intense and requires a higher dimensional parameter space, our proposed method reduces the computational complexity significantly, and accurately detects ellipses in realtime. We present a new method of detecting arc-segments from the image, based on the properties...
As adoption of system-level hardware design is increasing in industry and academia, accurate power estimation at this level is becoming important. In this paper, we present a system-level power estimation methodology, which is based on a high-level synthesis framework and supports sufficiently accurate power estimation of hardware designs at the system-level. For early and accurate power estimation,...
Accurate and efficient power estimation at higher-levels of abstraction is becoming increasingly important. However, tools and methodologies are lacking for such a task. In this paper, we present a methodology for accurate power estimation at high-level by reusing pre-existing verification or validation resources in the design flow. This novel methodology enables architectural exploration and design...
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