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Clock-gating is a well known technique to reduce dynamic power consumption of a hardware design. In any clock-gating based power reduction flow, automatic selection of appropriate registers and/or register banks is extremely time-consuming because power analysis is performed at the RTL or lower level. In a high-level synthesis (HLS) based design flow, to achieve faster design closure, one must be...
As adoption of system-level hardware design is increasing in industry and academia, accurate power estimation at this level is becoming important. In this paper, we present a system-level power estimation methodology, which is based on a high-level synthesis framework and supports sufficiently accurate power estimation of hardware designs at the system-level. For early and accurate power estimation,...
This article shows how design space exploration can be realized through high-level synthesis.It presents a case study of a hardware implementation of the advanced encryption standard (AES) Rijindael algorithm. Starting from algorithmic specification, it generate various architectures by using the C2R compiler.
Accurate and efficient power estimation at higher-levels of abstraction is becoming increasingly important. However, tools and methodologies are lacking for such a task. In this paper, we present a methodology for accurate power estimation at high-level by reusing pre-existing verification or validation resources in the design flow. This novel methodology enables architectural exploration and design...
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