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Accurate and efficient power estimation at higher-levels of abstraction is becoming increasingly important. However, tools and methodologies are lacking for such a task. In this paper, we present a methodology for accurate power estimation at high-level by reusing pre-existing verification or validation resources in the design flow. This novel methodology enables architectural exploration and design...
We have developed a fully integrated, miniaturized embedded stereo vision system (MESVS-I) which fits into a tiny package of 5 times 5 cm and consumes very low power (700 mA @ 3.3 V). The system consists of two small profile CMOS cameras, and a power efficient, dual-core embedded media processor, running at 600 MHz per core. The stereo-matching engine performs sub-sampling, rectification, pre-processing...
Embedded systems are becoming complex day by day and their increasing demand with shorter time-to-market is forcing designers to migrate to electronic system-level (ESL). One of the biggest issues with such battery-operated electronics is the power consumption. Facilitating power-aware architectural exploration at ESL requires a fast and accurate system-level power analysis capability. Existing frameworks...
Functional validation of System Level Models, such as those modeled with SystemC, is an important and complex problem. One of the problems in their functional validation is the test case generation with good coverage and higher potential to find faults in the design. We propose a coverage-directed test generation framework for system level design validation by combining the synchronous language ESTEREL,...
The real time embedded systems (RTES) project was created to study the design and implementation of high-performance, heterogeneous, and fault-adaptive real time embedded systems. The driving application for this research was the proposed BTeV high energy physics experiment, which called for large farms of embedded computational elements (DSPs), as well as a large farm of conventional high-performance...
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