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The following topics are dealt with: high level circuit design validation and test; multiprocessors; post-silicon validation; test generation; formal verification; coverage directed validation; multi-core design; and embedded systems.
In this paper, we propose the generalized de Bruijn graph as a reliable and efficient network topology for a Network-on-Chip (NoC) design. We also propose a reliable routing algorithm to detour a problematic (i.e., faulty or congested) link. Our experimental results show that the latency and energy consumption of generalized de Bruijn graph are much less with compared to Mesh and Torus, the two common...
Hierarchical testing requires the verification of individual processes followed by the verification of the interactions among processes. The large number of potential interactions between processes must be managed in order to make the testing process tractable. Fortunately, many potential interactions are actually infeasible and should be ignored during the verification process. Data dependency between...
In this paper we develop a framework for fast and accurate multiprocessor system performance simulation. Our simulation model generator generates simulation modules with accurate time deltas for software processes based on the intermediate representations generated by a compiler. The simulation modules are simulated as concurrent tasks in multiprocessor system performance simulation environment in...
This paper presents a tool for automatic generation of transaction level models (TLMs)for MPSoC designs using only C-code and graphical capture. The MPSoC platform is captured as a graphical net-list of components, busses and bridge elements. The application is captured as C processes mapped to the platform components. Once the platform is decided, a set of transaction level communication APIs is...
Multiprocessor System-on-Chip (MPSoC) has emerged as the most promising architecture for future embedded system designs, and Kahn Process Networks (KPN) have been shown to be an excellent solution to model applications for MPSoC because it allows maximum freedom in implementation. However, the effects of buffer sizing for KPN applications on MPSoC are not well investigated. Sizes for the bounded FIFOs...
In general, considerable time and resources are spent during pre-silicon verification phase to proactively minimize functional issues at first silicon. This is no different on the UltraSPARC T2 - the world's fastest commodity microprocessor. We deployed simulation, formal and emulation technologies coupled with solid methodology to cover all our bases, ensuring functional success of first silicon...
Recent IBM processors used in various computer systems including gaming systems are a very aggressive design, addressing three main challenges of the processor design -Memory wall, Power wall and ILP wall. To break these walls the some designs utilized multi threaded, multi core and yet high frequency. These kinds of designs increased the complexity of the test stream generation for processor verification...
CPU Post-Silicon functional validation is the last "guardian" logic-wise before delivering the product to the market. In each CPU generation, the challenges are larger due to increasingly complex architectures, budget constraints and shorter schedules. Success can be achieved just with the novel approaches across different validation teams, and with a complex of state-of-the-art validation...
This paper presents the item-missing error model. It stems from the analysis of real bugs that are collected in two market-oriented projects: (1) the AMBA interface of a general-purpose microprocessor IP core; (2) a wireless sensor network oriented embedded processor. The bugs are analyzed via code structure comparison, and it is found that item-missing errors merit attention. The test generation...
Recent improvements in design verification strive to automate the error-detection process and greatly enhance engineers' ability to detect functional errors. However, the process of diagnosing the cause of these errors and fixing them remains difficult and requires significant ad-hoc manual effort. Our work proposes improvements to this aspect of verification by presenting novel constructs and algorithms...
In order to help designers debug and verify a Gate-Level design that is generated from a Register-Transfer-Level (RTL) reference model, it is important to bridge the knowledge gap between the two levels of abstraction. In this paper, we present a comprehensive approach to establish correspondence of design objects between a Gate-Level implementation and its golden reference model specified at RTL...
Functional validation of System Level Models, such as those modeled with SystemC, is an important and complex problem. One of the problems in their functional validation is the test case generation with good coverage and higher potential to find faults in the design. We propose a coverage-directed test generation framework for system level design validation by combining the synchronous language ESTEREL,...
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