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This paper evaluates four designs of XOR employing our previously presented two-phase clocked adiabatic static CMOS logic (2PASCL) circuit techniques. 2PASCL XOR, which demonstrates the lowest power dissipation, is used for the 4 × 4-bit array 2PASCL multiplier. From our simulation results, at transition frequencies of 1 to 100 MHz, the 4 × 4-bit array 2PASCL multiplier shows a maximum of 55% reduction...
Simultaneous switching noise (SSN) causes signal degradation to the high-speed interfaces among CMOS VLSIs. To achieve SSN simulation with a high accuracy, accurate models for chips, packages and printed circuit boards (PCBs) are required. However, such accurate simulation models are not currently available, since chip vendors do not release the value of on-chip capacitance and the detailed package...
Electronic pre-equalization for 43 Gb/s DQPSK has been demonstrated for the first time. Waveform distortion caused by bandwidth narrowing to 18.1 GHz by cascaded 10 Gb/s ROADMs has been adequately pre-equalized by a SiGe-BiCMOS LSI with 6-bit, 43 GS/s digital-to-analog converters.
This paper demonstrates some fundamental logic gates employing two phase clocked adiabatic static CMOS logic (2PASCL) circuit techniques. We design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology using SPICE implemented using 0.18 ??m CTX CMOS technology. For NOT circuit, analytical and simulation values are compared. From the simulation results, we find that 2PASCL...
This paper demonstrates the low energy operation of 4-bit ripple carry adder (RCA) employing two phase clocked adiabatic static CMOS logic (2PASCL) circuit techniques. We evaluate NOT, NAND, XOR and NOR logic gates on the basis of the 2PASCL topology using SPICE implemented using 0.18 ??m CTX CMOS technology. For NOT circuit, analytical and simulation values are compared. By removing the diode from...
This paper demonstrates the low-energy operation of a two-phase clocked adiabatic static CMOS logic (2PASCL) on the basis of the results obtained in the simulation of a 4-bit ripple-carry adder (RCA) and D-flipflop employing 2PASCL circuit technology. Two-phase unsymmetrical power supply clocks are introduced to increase the logic transition level. Energy dissipation in the unsymmetrical clocked 2PASCL...
This paper demonstrates the low-energy operation of a two-phase clocked adiabatic static CMOS logic (2PASCL) on the basis of the results obtained in the simulation of a 4-bit ripple-carry adder (RCA) employing 2PASCL circuit technology. Energy dissipation in the 2PASCL RCA is 71.3% lesser than that in a static CMOS RCA at transition frequencies of 10-100 MHz.
In this paper, we propose a LC resonator circuit using Hara's active inductor for adiabatic logic. The proposed circuit consists of four MOS-transistors Colpitts oscillator and an active inductor. This circuit require no inductor and can be produced two-phase sinusoidal clocking. From the simulation results, we show that the proposed circuit was operated as a 10 MHz, 3 V peak-to-peak LC resonant oscillator.
This paper describes a Pulse-Width Modulation (PWM) pre-emphasis technique which utilizes time-domain information processing to increase the data rate for a given bandwidth of interconnection. The PWM pre-emphasis method does not change the pulse amplitude as for conventional FIR pre-emphasis, but instead exploits timing resolution. This fits well with recent CMOS technology trends toward higher switching...
This paper presents a new equalization technique based on a pulse-width modulation (PWM) pre-emphasis method which utilizes time-domain information processing to increase the data rate for a given bandwidth of VLSI interconnection. The pre-emphasis method does not change the pulse amplitude as for conventional FIR pre-emphasis, but instead exploits timing resolution. This fits well with recent CMOS...
The new SET characterization technique for 0.15 mum Fully Depleted CMOS/SOI digital circuitries was investigated using SPICE and TCAD simulations. The SPICE simulation with a switch can readily reproduce the corresponding SET voltage response for a certain LET. This technique is valid as an alternative in all load and complementary transistor conditions, irrespective of the presence of a plateau region...
The 0.18 /spl mu/m CMOS direct-conversion dual-band triple-mode WLAN transceiver covers 2.4 to 2.5 GHz and 4.9 to 5.95 GHz and draws 78 mA in the receive mode and 76 mA in the transmit mode, from a 1.8 V supply both at 2.4/5 GHz. The system NF of 3.5/4.2 dB, the sensitivity of -93/-94 dBm for a 6 Mbit/s OFDM signal, and the EVM of 3.2/3.4% are obtained at 2.4/5.2 GHz.
A 5-V CMOS chip set used for an integrated services digital network (ISDN) U-interface transceiver is described which accomplishes 2B+D channel (144-kb/s) transmission using a 2B1Q line code based on echo cancellation over existing two-wire subscriber loops. The three-chip set consists of an analog front end (AFE), an echo canceler (ECD) and a receiver (RCV). The last two are digital signal processors...
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