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The total performance of low-k/Cu interconnects featuring short turnaround-time (TAT) silylated scalable porous silica (Po-SiO, k = 2.1) with high porosity (50%) is demonstrated. The TAT for the film formation process including silylation treatment is about 25% reduced by adding a promoter, causing reinforcement of the film. Applying this improved Po-SiO, a 140-nm-pitch dual-damascene structure is...
A comprehensive study of low-k/Cu integration featuring short TAT (turnaround time) silylated scalable porous silica (Po-SiO, k=2.1) with high porosity (50%) is presented. The TAT for silylation is about 25% reduced by adding a promoter, causing reinforcement of the film. Applying this improved Po-SiO, 140 nm pitch dual damascene structure is successfully achieved. The wiring capacitance showed 10%...
The influence of phosphorus at the floating gate (FG)/tunnel oxide interface on the FLASH memory data retention characteristics is investigated. By measuring the electrical characteristics of memory cells and MOS capacitors, it was found that there is a close relationship between the memory cell data retention and stress induced leakage current (SILC). Lowering the phosphorus density in the FG is...
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