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A miniature 35-110 GHz modified reflection-type BPSK modulator using a 65-nm CMOS process is presented in this paper. The core area of the modulator is only 150 times 370 mum2 due to a compact broadside coupler and a 180deg hybrid used in the BPSK modulator. The BPSK modulator demonstrates a modulation bandwidth of wider than 1 GHz, an error vector magnitude (EVM) of within 10%, a dc offset of better...
This paper presents a 65nm low power technology offering a dual gate oxide process, multiple Vt devices at a nominal operating voltage of 1.2V, a nine level hierarchical Cu interconnect back-end of line process with low k dielectrics and 0.676mum2 and 0.54mum 2 SRAM cells, optimized for performance and density, respectively. The key focus of this technology has been low cost, process simplicity and...
This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low power applications. Utilizing plasma nitrided gate oxide, off-set and slim spacers, advanced co-implants, NiSi and low temperature MOL process, well designed NMOSFET and PMOSFET achieved significant improvement from the previous generation, especially PMOSFET has demonstrated...
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