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We have developed a 2-bit 32 GS/s soft decision LSI in 0.13 μm SiGe-BiCMOS. The LSI includes a flash type Analogue-to-Digital converter and an encoder which outputs the soft decision results, which are a hard decision bit and a confidence bit for strong Forward Error Correction. We have confirmed that the LSI has 25 mVpp sensitivity and the LSI enables 2 dB better FEC coding gain than hard decision.
Electronic pre-equalization for 43 Gb/s DQPSK has been demonstrated for the first time. Waveform distortion caused by bandwidth narrowing to 18.1 GHz by cascaded 10 Gb/s ROADMs has been adequately pre-equalized by a SiGe-BiCMOS LSI with 6-bit, 43 GS/s digital-to-analog converters.
The concatenation of LDPC and RS codes has been demonstrated using a real-time FPGA prototype. A net coding gain of 9.0dB for 31.3-Gb/s was achieved with 20.5% redundancy for an input BER of 10−2.
We have developed a 2-bit 32 Gsample/s soft decision LSI for low-density parity-check code FEC at 100 Gb/s in 0.13 mum SiGe-BiCMOS which generates confidence bit with 25 mVpp sensitivity.
For the 45 nm beyond advanced LSI mass-production, accurate dose and beam angle control for the implantation process is highly required. For the purpose the ion beam size and angle monitor was developed and installed in EXCEEDS 000AH new version medium current ion implanter.. The measured results shows the beam size and angle increased at the beam energy decreased, especially for the Y direction beam...
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