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The stress of Cu interconnects embedded in advanced ultra-low-k (ULK) dielectrics was studied for different porosities. Interconnects formed a high porosity material result in a lower stress due to relaxation in the plane. This effect is less significant for narrow lines, where in-plane relaxation is reduced by the dense narrow spacing. The stress in isolated lines was found to be independent of dielectric...
The time and temperature dependence of Stress-Induced-Voiding below and in copper VIA's with a diameter of 80 nm integrated in a k = 2.5 material was studied. The focus was on the early phase of the voiding process. To accelerate the degradation, test structures with big metal plates below and/or above the VIA were used. We found two degradation mechanisms in which one dominated below and the other...
The temperature dependent driving force for stress induced voiding of Cu dual damascene interconnects has been studied using finite element modeling. Both 2D axisymmetric and 3D models have been investigated. Interconnect test structures have been simulated at temperatures ranging from 25 to 300degC and a stress free temperature for the structure is demonstrated, consistent with analytical modeling...
This work reports the results of a mechanical sensor to monitor stress in 100 nm critical dimension Cu interconnects. Existing methodology developed for larger scale Al sensors is discussed and evaluated for Cu/SiO2 and Cu/Low-k integration schemes. New sensor release methods are then developed and the Cu sensor is demonstrated in single and dual damascene technology. We also demonstrate the sensor...
In this paper we investigate the reliability of Cu contacts with both Ta and W based barriers using thermal and electrical stressing. The Ta based barrier showed superior resistance to electrical stressing, with a time-to-failure approaching that of the W-plug reference and a via like failure mode. However early fails reduce the t50 due to high process induced stress imposed by the pre-metal dielectric...
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