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A wideband auxiliary receiver embeds a band-reject N-path filter in the low-noise amplifier to improve the compression point. The receiver has high input impedance and it can be placed at the transmitter output without loading effects. Implemented in a 28nm CMOS technology it occupies 0.12mm2 active area and it can withstand up to +4 dBm QPSK modulated 20 MHz signal with less than 1-dB noise degradation...
VDSL2 transceivers use a wide analog bandwidth to achieve bit-rates in excess of 200 Mb/s. For standard 6-band VDSL2, 30 MHz bandwidth is required, comprising three up-stream and three down-stream signals. Since discrete multi tone (DMT) modulation is used, distortion components for the signal chain have to be below -65dBc to fully exploit 15b-per-tone bit loading. The presented AFE is implemented...
A low-IF very compact low power quadrature receiver for ZigBee applications is presented. The receiver saves area and power with a quadrature self oscillating mixer based on high Q bond-wire inductors. The prototype, integrated in CMOS 90 nm, provides 76 dB of maximum voltage gain, with a 10 dB noise figure, an IIP3 of -13 dBm and a phase noise of -124 dBc/Hz @ 3.5 MHz with an active area of only...
A 35mW- 3.6mm2GPS radio has been integrated in a 0.18µm CMOS process. Housed in a standard VFQFPN52 package, the GPS radio needs just a few external passive components for the input matching network and one external reference for the Synthesizer. The GPS receiver chain down-converts a Coarse/Acquisitions L1 signal with NF-5.3dB, conversion gain 81dB, Image Reject > 32dB. The synthesizer features...
This paper reports on a telephone chip that performs all the basic functions of a speech circuit using only two external components. Precision filtering using Switched Capacitor (SC) techniques is used to implement on-chip impedance termination, hybrid with sidetone cancellation and DC characteristics starting from a single 1% external resistor. Better than 30 dB matching is achieved without any external...
A four stages fully-differential amplifier that uses a double nested Miller compensated structure to lower harmonic distortion is presented. With a single 5V supply power dissipation is 10mW and THD is ??83dB for a 6Vpp differential output signal at 10kHz and a load of 50??. With 8?? load and 10kHz, 4Vpp output signal, THD is ??68dB. The chip area is 1000mils2 in a 1.5?? n-well CMOS technology.
A CMOS differential buffer amplifier for ISDN applications is reported. The chip operates from a single 5 V power supply and can deliver a 6 Vpp 80 kHz signal into a load of 100 ohm and/or 300 pF with a THD of about 0.25 %. The circuit main feature is its PSRR which remain practically constant from de to several hundred kHz around - 75 dB for both positive and negative supplies with the common mode...
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