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An oversampled cascaded-modulator audio DAC architecture to reduce out-of-band noise is presented. Pulse-width modulation combined with an analog-FIR filter is used to reduce the impact of circuit mismatch and dynamic glitch errors. Implemented in 45 nm CMOS as a current-steering DAC, the 0.045 mm2 chip delivers 110 dB DR while consuming 0.5 mW.
A single-amplifier double-sampling second-order /spl Delta//spl Sigma/ ADC with 5-level quantization is implemented in 90nm CMOS. To alleviate the capacitor mismatch issues in double sampling techniques, a single capacitor method is introduced, achieving 63dB peak SNDR and 66dB DR in a 1.94MHz bandwidth while consuming 1.2mW from a 1.2V supply.
A fourth-order 1b CT /spl Delta//spl Sigma/ converter using a two-amplifier loop and a 267MHz sampling frequency is implemented in 90nm CMOS. A double-loop architecture couples passive poles with a reduced number of active blocks to improve area and power while achieving 86dB peak SNR over a 600kHz band.
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