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The purpose of this paper is to present a new method and structure for the automatic configuration of a digital system to unknown delays in synchronous input data channels. The method makes possible to restore synchronism in node-to-node communication. Synchronism may be lost due to different delays introduced by the various communication channels. The proposed method allows differences in the channel...
The purpose of this paper is to present a novel built-in Clock Domain Crossing (CDC) test and diagnosis methodology for Globally Asynchronous, Locally Synchronous (GALS) systems. The methodology allows design and prototype validation, low maintenance and repair costs, and production / lifetime at-speed test. Moreover, high resolution diagnosis is obtained, to identify which device(s) and/or communication...
The purpose of this paper is to present a new robust methodology for synchronous communications in a BUS, connecting multi-clock domains. Traditionally, when robust solutions are needed, an asynchronous communication is used. However, the low transfer rates associated with asynchronous solutions make them inadequate for high performance digital systems. On the other hand, synchronous communications...
The data concentrator card (DCC) is part of the readout electronics of a particle physics detector. The DCC project is a multi-project project involving high-speed design, built-in testability, data processing with data reduction techniques, low-jitter clock distribution, power supply regulation and filtering and implementation of multiple FPGAs on a 9U multilayer printed circuit board. The DCC collects...
The Clear-PEM detector is a positron emission mammography scanner based on a high-granularity avalanche photodiode readout with 12 288 channels. The front-end sub-system is instrumented with low-noise 192:2 channel amplifier-multiplexer ASICs and free-running sampling ADCs. The off-detector trigger, implemented in a FPGA based architecture, computes the pulses amplitude and timing required for coincidence...
The clear-PEM detector is a positron emission mammography scanner based on high-granularity avalanche photodiodes readout with 12 288 channels. The front-end sub-system is instrumented with low-noise 192:2 channel amplifier-multiplexer ASICs and free-running sampling ADCs. The off-detector trigger, implemented in a FPGA based architecture, computes the pulses amplitude and timing required for coincidence...
The main aspects of the design and test (D&T) of a reconfigurable architecture for the data acquisition electronics (DAE) system of the clear-PEM detector are presented in this paper. The application focuses medical imaging using a compact PEM (positron emission mammography) detector with 12288 channels, targeting high sensitivity and spatial resolution. The DAE system processes data that comes...
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