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A 1.35 ns random access and 1.7 ns-random-cycle SOI embedded-DRAM macro has been developed for the POWER7™ high-performance microprocessor. The macro employs a 6 transistor micro sense-amplifier architecture with extended precharge scheme to enhance the sensing margin for product quality. The detailed study shows a 67% bit-line power reduction with only 1.7% area overhead, while improving a read zero...
Largely due to cooling power consumption needed for their thermal management, data centers consume over 2% of the electricity produced in the United States. A fundamental understanding of data center energy management is both environmentally and economically important. This paper develops a model of data center energy utilization for thermal management based on thermo-fluid first principles. The model...
This paper presents a 1.7 ns-random-cycle SOI embedded-DRAM macro developed for the POWER7?? high-performance microprocessor and introduces enhancements to the micro-sense-amplifier (??SA) architecture. The macro enables a 32 MB on-chip L3 cache, eliminating delay, area and power from the off-chip interface.
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