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This paper describes back-gate biasing scheme using independent-gate controlled asymmetrical (n+/p+ polysilicon gates) FinFETs devices and its applications to 6-T and 8-T SRAM. Row-based above-VDD/below-GND bias is applied to the back-gates of the access and pull-down cell nFETs to enhance the read/write performance, reduce standby leakage, and mitigate process (VT) variability. The application of...
This paper presents novel asymmetrical SRAM cell topologies in double-gate technology. These cells utilize the independent-gate control to overcome the limitation of conventional device sizing for stability improvement in asymmetrical SRAM cells. We show that optimal READ stability, where the READ stability approaches the HOLD stability, can be achieved with the proposed scheme. Mixed-mode device/circuit...
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