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Power delivery network (PDN) design is one of the most critical challenges in 3D Integrated Circuits (IC) design. In existing studies, to ensure the robustness of the 3D PDN, the number of TSVs was always increased inefficiently to mitigate the IR-drop and power noise. However, the overhead for connections is a crucial obstacle to the development of 3D ICs. Consequently, an efficient TSV topology...
Through-silicon via (TSV) could provide vertical connections between different dies in three-dimensional integrated circuits (3D ICs), but the significant silicon area occupied by TSVs may bring great challenge to designers in 3D clock tree synthesis (CTS) because only few whitespace blocks can be used for clock TSVs after floorplan and placement. Unlike most of the published previous works that ignore...
Three dimensional integrated circuits (3D ICs) are currently being developed to improve existing 2D designs by providing smaller chip areas and higher performance and lower power consumption. However, before 3D ICs become a viable technology, the 3D design space needs to be fully explored and 3D EDA tools need to be developed. To help explore the 3D design space and help fill the need for 3D EDA tools,...
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