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In this paper, the design space, including fin thickness (Tfin), fin height (Hfin), fin ratio of bit-cell transistors, and surface orientation, is researched to optimize the stability, leakage current, array dynamic energy, and read/write delay of the FinFET SRAM under layout area constraints. The simulation results, which consider the variations of both Tfin and threshold voltage (Vth), show that...
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