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Non-blocking caches, which are commonly utilized in modern out-of-order processors, could handle multiple outstanding memory requests simultaneously to reduce the penalties of long latency cache misses. Memory level parallelism (MLP), which refers to the number of memory requests concurrently held by Miss Status Handling Registers (MSHRs), is an indispensable factor to estimate cache performance....
Evaluating cache performance is becoming critically important to predict the overall performance of out-of-order processors. Non-blocking caches, which are very common in out-of-order CPUs, can reduce the average cache miss penalty by overlapping multiple outstanding memory requests and merging different cache misses with the same cacheline address into one memory request. Normally, memory-level-parallelism...
The Advanced Encryption Standard (AES) is specified as the cipher algorithm in IEEE 802.15.4 protocol and other industrial wireless networks protocols based on IEEE 802.15.4. But the huge computation overhead of the traditional AES implementations makes AES hard to be performed on the resource-constrained industrial wireless nodes. Although the software implementations based on 4 lookup tables and...
Industrial wireless network has a high certainty, and its security is an important issue. As a normal secure transmission mechanism in most of MAC layers of industrial wireless networks, CCM has a huge computation overhead. Due to the constrained resource in the nodes of industrial wireless network, it is hard to achieve a tradeoff between delay and security when implement CCM. In order to help the...
Frequent item set mining is an important researching area in data mining and Eclat is a typical and high performance frequent item set mining algorithm. However, the large numbers of sorted-set intersection computation in the algorithm limit the performance of the algorithm seriously. FPGA is a low-power and high-performance computing platform that has been applied to accelerate parallel data mining...
Because of the high computation demand for multimedia applications like video decoding, there is a need to develop flexible and high performance reconfigurable computing architectures. Taking video decoding algorithm as an example, we propose a reconfigurable computing realization solution of multimedia application. Based on the analysis of parallelism in video decoding algorithm, a hardware platform...
In this paper, procedural texture mapping based on Perlin noise is firstly implemented and simulated in Matlab. And then the design is converted from float-point to fix-point in Simulink. Using the system modeling tool, System Generator from Xilinx company, the noise function can be directly mapped into FPGA hardware. From the experimental results, various graphical textures can be implemented in...
As broadband network services are becoming more and more abounding, the QoS(quality of service) of broadband networks has caught the attention of many professional people. Sometimes, the resource-constrain of embedded systems affects the quality of the multimedia services seriously. To solve this problem, this paper proposes an effective scheme for buffer management, which is named QoSBuf.. This scheme...
Traditional CPU instructions provide limited support to the byte permutation operation which is frequently used in the various symmetric encryption algorithms. Due to this reason, researcher Ruby B. Lee at Princeton University presented the byte permutation instructions and proved that the byte permutation instructions played an important role on improving the performance of cryptographic algorithms...
Since the latest IC technology supports the integration of soft or hard CPU cores with dedicated logic on a single silicon chip, it leads FPGA into embedded system design and arouses the innovation of design methodology. In this paper, a general introduction of embedded system and the FPGA-based SOPC development are discussed. The FPGA-based embedded system can contain microprocessor IP cores and...
A flash storage system based on cable modem is implemented. On the hardware hand, a flash controller is designed using cache and queue technology, and realizes burst read from flash by a simple set associative cache, and implements asynchronous write to flash by FIFO queue. On the software hand, we revise CFI on MTD so that flash access processes are scheduled by the way of interrupt instead of continuous...
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