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We have investigated a fully depleted double-gate 1-T DRAM cell device which has SONOS type storage node on control gate for nonvolatile memory function. Due to enlarged hole capacity by the large storage node and source/drain junction depth control in the floating body, we could improving data retention time, Is,(write"1")/Is,(write"0") and device scalability. Proposed device...
In this paper, the authors proposed a new double-gate 1-T DRAM cell device which has nonvolatile memory function on one gate. Due to enlarged hole capacity in the floating body by the nonvolatile function, high write1 and low write0 current (high ??Vth) could be done. By adopting non-overlap structure, device scalability was improved. Proposed device could be a very promising candidate for a future...
In this paper, design considerations for the n+/p+/n+ gate bulk FinFET in sub-50-nm technology nodes is extensively studied through 3D device simulation. For the comparison of electrical characteristics of n+/p+/n+ gate bulk FinFET, the electrical characteristics of p+/n+ gate bulk FinFET were also studied. The electrical characteristics of devices with different n+ gate lengths (Ls) and fin body...
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