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A high performance embedded DRAM with deep trench capacitor and high performance SOI logic has been deployed in 45nm and 32nm technology nodes. Following a yield ramp of the sub-2ns latency 45nm technology, we present, for the first time, a 32nm eDRAM technology fully compatible with high performance logic with high-?? metal gate access transistor and high-?? node dielectric for the deep trench storage...
In this paper, we investigate the retention time distribution of IBM's 65nm node embedded DRAM. We demonstrate that subthreshold current is the dominant leakage mechanism that determines data retention time, and the retention distribution can be attributed to array Vt variation. Based on this study, we present a new technique for characterization of across-chip Vt variation. The Vt median value and...
A 65 nm prototype embedded DRAM macro on partially depleted SOI (PD-SOI) substrate capable of <2. 0ns latency and the enabling cell technology have been described previously [1,2]. In this paper, we focus on the cell design and optimization for best retention and performance which have been extended to the 45 nm node.
Two integration schemes for hybrid crystal orientation technology using direct silicon bonded (DSB) substrates and solid phase epitaxy (SPE) processes have been implemented. The shallow-trench-isolation (STI) before SPE approach suffers from trench-edge defects formed at STI edges, which causes high leakage current. The SPE-before-STI approach allows removal of edge defects of SPE by STI. SRAM in...
The authors present a 65nm embedded DRAM cell (0.127 μm2 cell size) on unpatterned SOI fabricated using standard high performance SOI technology with dual stress liner (DSL). The cell utilizes a low-leakage 2.2-nm gate oxide pass transistor and a deep trench capacitor. A trench side wall spacer process enables a simplified collarless process. Connection to the buried plate is realized by silicided...
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