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Negative capacitance field effect transistors is found to be a promising option for low power VLSI devices in the advanced technology node. In this article, through extensive numerical simulation, we report the scaling effect of ferroelectric gate stack, channel thickness and gate length on electrostatic integrity, DC, analog and RF performance of InGaAs quantum well MOS transistor. The different...
With use of III‐V material in the channel region of a metal‐oxide‐semiconductor (MOS) transistor, interface buffer layers above and below the channel region are necessary to reduce several sources of scattering of the inversion charge carriers. This work presents a detailed analysis of effect of scaling down thickness of the top buffer layer of a buffered InAs‐OI‐Si metal‐oxide‐semiconductor field...
Role of high-κ spacer of Asymmetric underlap double gate MOS transistor on SRAM performance is systematically investigated with the help of two-dimensional device simulator. SRAM cell designed using high-κ spacer MOS device shows significant improvement in hold, read and write noise margin. However, due to increase in parasitic capacitance, delay performance of SRAM cell is slightly degraded. Leakage...
InGaAs (and its variant) appears to be a promising channel material for high-performance, low-power scaled CMOS applications due to its excellent carrier transport properties. However, MOS transistors made of this suffer from poor electrostatic integrity. In this work, we consider an underlap ultra thin body (UTB) InAs-on-Insulator n-channel MOS transistor, and study the effect of varying the gate-source/drain...
Impact of high-κ spacer in Asymmetric underlap double gate MOS transistor is systematically investigated with the help of a two dimensional device simulator. A significant improvement in ON current, transconductance and intrinsic gain is observed in the device using high-κ spacer material. However due to higher capacitances, device with high-κ spacer shows smaller unity gain cut-off frequency compared...
Influence of operating temperature on short channel characteristics, analog and RF performance of Double gate MOS transistor is systematically investigated with the help of a 2-Dimensional commercial device simulator. Temperature compensation point is observed in the transfer characteristics of device. Overall improvement in Analog/RF Figure of Merit is observed at low temperature operation.
Impact of gate underlap in nanoscale ultrathin body Germanium-on Insulator (Ge-OI) MOS transistor is investigated with the help of well calibrated TCAD simulation. Due to higher permittivity of Ge, MOS device with no underlap shows poor short channel immunity. While increasing underlap length significant improvement in short channel immunity is observed. Due to higher channel resistance reduction...
In this paper, a five transistor voltage adder, consisting of a flipped voltage follower devised to work in low voltage rail, has been used as the main building block for designing an analog multiplier. Four of such cells have been used for biasing and signaling. This Multiplier has been designed using GPDK 90nm CMOS technology and simulated in Cadence Spectre environment. The supply voltage has been...
In this paper with the help of technology computer-aided design (TCAD) simulation we present comparative study of analog and RF performance of an UTBOI- Si Substrate MOS transistor for two different channel materials: Si and InGaAs (with and without buffer). We have analyzed different analog and RF figure of merits such as transconductance, transconductance generation factor, output conductance, intrinsic...
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