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To minimize the access latency of set-associative caches, the data in all ways are read out in parallel with the tag lookup. However, this is energy inefficient, as only the data from the matching way is used and the others are discarded. This paper proposes an early tag lookup (ETL) technique for L1 instruction caches that determines the matching way one cycle earlier than the cache access, so that...
Large on-chip caches with uniform access time are inefficient to be used in multicore processors due to the increasing wire delays across the chip. The Non-Uniform Cache Architecture (NUCA) is proved to be effective to solve the problem of the increasing wire delays in multicore processors. For real-time systems that use multicore processors, it is crucial to bound the worst-case execution time (WCET)...
As transistor feature size scales down, soft errors in combinational logic because of high-energy particle radiation is gaining increasing concerns. In this paper, a soft error mitigation method based on accurate mathematical modeling of SER and addition of non-invert functionally redundant wires (FRWs) is proposed. In the proposed method, the factors which have significant influences on SER because...
Reconfigurable architectures, such as Field-Programmable Gate Arrays (FPGAs), have become one of the key digital circuit implementation platform over the last decade due to its short time-to-market and low design cost. However, the major bottlenecks of FPGAs are their low logic utilization rate and long reconfiguration latency. In order to overcome these limitations, novel dynamically reconfigurable...
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