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A 3D stacked network-on-chip (NOC) promises the integration of a large number of cores in a many-core system-on-chip (SOC). The NOC can be used to test the embedded cores in such SOCs, whereby the added cost of dedicated test-access hardware can be avoided. However, a potential problem associated with 3D NOC-based test access is the emergence of hotspots due to stacking and the high toggle rates associated...
At-speed testing of deep-submicron or nano-scale integrated circuits (IC) consumes excessive power and creates hotspots and temperature gradient in the chip-under-test. The problem worsens for 3D ICs, where heat dissipation across layers is more unbalanced. These hotspots in a circuit often cause severe degradation of performance and reliability, as a rise in temperature can introduce an extra delay...
The rapid growth in CMOS technology enables the technology of three-dimensional (3D) SoCs to be a promising approach for extending Moore's Law. Although the benefits supplied by 3D integration, managing test architecture design and reducing test cost are crucial challenges. Some powerful automatic test equipments (ATEs) that support different speed rate channels come into people's vision. In this...
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