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P-MOSFETs with HfO2 gate dielectric and TiN metal gate were fabricated on compressively strained SiGe layers with a Ge content of 50 at.% and electrically characterized. The devices showed good output and transfer characteristics. The hole mobility, extracted by a split C-V technique, presents a value of ~200 cm2/V·s in the strong inversion regime.
CMOS devices with high-k/metal gate stacks have been fabricated using a gate-first process flow and conventional stressors at gate lengths of 25 nm, highlighting the scalability of this approach for high performance SOI CMOS technology. AC drive currents of 1630muA/mum and 1190muA/mum have been demonstrated in 45 nm ground-rules at 1V and 200nA/mum off current for nFETs and pFETs, at a Tinv of 14...
A new structure combining a beam-diaphragm structure and a SOI-on-cavity substrate was proposed in this paper. Both high sensitivity and good linearity could be achieved due to the stress concentrated structure.
Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest Tinv (≪12??) for BE nFET devices to-date, consistent with simulations showing the need for ≪14??...
Starting with the 45 nm node, a tradeoff between performance and density exists that become more severe at the 32 nm node. An in-depth analysis of the impact of pitch and increased parasitics on device performance in the 32 nm node is presented. To counteract these effects, reduction of parasitics, gate length scaling, and aggressive stress engineering are necessary. Optimized layout using a "relaxed-pitch"...
In this work, two-dimensional numerical device simulations and 6-stage inverter chain delay calculations are done to examine whether aggressive channel length scaling continually provides transistor performance gain and whether metal gates (MG) offer potential for device scaling over poly gate (PG) for high performance (HP) applications. Our simulation show that for HP application (1) there is an...
X-ray and Co-60 irradiations caused large differences in charge buildup in SOI buried oxides because of the various electron-hole charge yield and dose enhancement effects. Dose enhancement effects are monitored with standard SOI NMOS transistors by measuring back-gate threshold shifts due to oxide-trapped charge. We have demonstrated that the device response to X-ray radiation can be used to predict...
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