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Silicon nanowire transistor with side-gate and back-gate has been fabricated by electron beam lithography combined with dry oxidation on a doped silicon-on-insulator wafer. The effects of back-gate and side-gate on the properties of single electron transport were investigated by measuring the channel current as function of the applied gate voltages. The tunable single electron effect and Coulomb oscillations...
Capacitance-voltage (C-V) and frequency dependent conductance-voltage (G-V) measurements have been carried out to investigate the charging and discharging effect induced by interface states and nanocrystalline Si (nc-Si) in floating gate MOS structures. Distinct conductance peaks are observed in the G-V curves for the floating gate with and without nc-Si dots. Based on the calculation of interface...
The nc-Si nonvolatile memory devices with high performance have been fabricated by using general CMOS techniques. High resolution transmission electronic microscope (HRTEM) shows that the average size of nc-Si is 8 nm and its density is 3×1011/cm2. The performance of programming/ erasing and retention time is mainly depending on the quality and thickness of tunnel layer and control layer. The results...
Size-controlled nanocrystals (Si NCs) in floating gate MOS structure have been fabricated by thermal annealing of Si-rich SiNx layers with high ratio of Si/N. High resolution transmission electronic microscopy (HRTEM) reveals the size of Si NCs can be controlled by varying the thickness of Si-rich SiNx layer. Based on the analysis of XPS and Raman measurement, the relation between the size of Si NCs...
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