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We developed the new control gate (CG) material and structure in order to overcome scaling limitation beyond 20nm NAND flash cell. New CG material can achieve excellent gap-fill without void and improvement of the Gate CD Gap (GCG). And also, by using new CG material, CG depletion between floating gate (FG) can be improved. As a result, gate coupling ratio, bit-line (BL) interference and tail-cell...
ReRAM has been researched as a promising candidate for diverse NVM application [1]. Still switching mechanism and classification are not clear, there are simply two kinds of switching polarity: unipolar and bipolar. Considering distribution, operation margin and so on, bipolar switching looks much attractive than unipolar. Along with a selective device, polarity of switching could make the architecture...
Multi-level NAND flash memories with a 20nm design rule have been successfully developed for the first time. A 20nm rule wordline (WL) and bitline (BL) direction have been realized by Spacer Patterning Technology (SPT) of ArF immersion lithography. Key integration technologies include WL airgap with separate gate etch process and optimized control gate (CG) poly deposition process. In addition, many...
Vertical double gate floating body (FB) Z-RAM memory cell technology fabricated on a recess gate DRAM technology is presented. Cell operating voltage of 0.5V with comparable static retention and > 1000× improvement in dynamic retention is reported. The reported vertical double gate FB cell is the cell with the lowest operation voltage reported to date.
With the advance of wireless communications technology, home automation based on home networks has regained attention. This paper proposes a wireless network protocol and a control device, which make it possible to control legacy home appliances in an interactive way. The proposed wireless network protocol provides a bidirectional communication channel between a gateway and control devices. The control...
RTS (random telegraph signal)-like fluctuation in Gate Induced Drain Leakage (GIDL) current of Saddle-Fin (S-Fin) type DRAM cell transistor was investigated for the first time. Furthermore, two types of fluctuation which have apparently different ??high (average time duration of high leakage state) to ??low (average time duration of low leakage state) ratio were investigated, and it was found that...
The operating characteristics and retention times of floating body cells and arrays using Z-RAMreg technology fabricated on a 50 nm DRAM process are presented. For the first time, data retention time longer than 8 s at 93degC and 1.6 V wide programming window are obtained on floating body cells as small as 54 nm times 54 nm. These results demonstrate the suitability of floating body memories for DRAM...
44 nm feature sized 8F2 1Gb DRAM is fully integrated and functioned for the first time with the smallest cell size of 0.015 um2. A novel cell-transistor structure and new DRAM process technologies are developed. In order to control the threshold voltage uniformity and body-bias sensitivity of saddle-fin cell-transistor, the channel doping profile and saddle-fin geometric dependency were analytically...
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