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Custom ESD protection without increasing loading capacitance is demonstrated for transmitter (TX) and receiver (RX) pins of the Xilinx Zynq UltraScale+ Microprocessor System-on-Chip (MPSoC) transceivers. Optimized T-coil cancellation was applied at a 32 Gb/s bit rate. Fast and reliable verification of the custom ESD design was developed based on Calibre PERC schematic checking combined with Calibre...
A high-speed back-biased CMOS EEPROM technology and its application to Programmable Logic Devices (PLDs) will be described. Several key features have allowed the fabrication of a next generation high performance EECMOS PLD; the use of two independent families of transistors for the high voltage programming and read paths, the application of back-bias and careful optimisation of a double-polysilicon...
This paper will describe a modular technology which uses a novel integration scheme to include double poly EEPROM, single poly EPROM and an interpoly capacitor. The single poly EPROM [1] has been adopted to simplify the integration issues; the three modules (EEPROM, EPROM and A/D) can be combined in any combination without affecting their electrical performance.
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