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This paper presents a robust energy/area-efficient receiver fabricated in a 28-nm CMOS process. The receiver consists of eight data lanes plus one forwarded-clock lane supporting the hypertransport standard for high-density chip-to-chip links. The proposed all-digital clock and data recovery (ADCDR) circuit, which is well suited for today’s CMOS process scaling, enables the receiver to achieve low...
A large doppler frequency shift will be produced under high dynamic environment,and GPS receiver cost longer time to capture satellite signals. That is a great drawback to some high dynamic carrier especially to some high-speed guided weapons. The paper proposed an acquisition algorithm aided by inertia information under high dynamic environment. Here the real-time speed and position of carrier is...
A quarter-rate forwarded-clock receiver utilizes an edge-rotating 5/4X sub-rate CDR for improved jitter tolerance with low power overhead relative to conventional 2X oversampling CDR systems. Low-voltage operation is achieved with efficient quarter-rate clock generation from an injection-locked oscillator (ILO) and through automatic independent phase rotator control that optimizes timing margin of...
This paper presents an energy/area-efficient forwarded-clock receiver fabricated in a 28nm CMOS process. The receiver consists of 8 data lanes plus one forwarded-clock lane, and adopts a novel all-digital clock and data recovery (CDR) using a delay-locked loop (DLL). The all-digital DLL with calibration can generate accurate multiphase clocks for both duty-cycle correction and the data recovery in...
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