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This paper presents a sub-1V dynamic comparator with cross-coupled latches at multi-GHz operation. The low-voltage cross-coupled latches structure with a separated tail current can be used to optimize the speed and the offset in the latched stage, respectively. A high speed readout circuit is also proposed to further enhance the speed of the comparator. With BER=109, the comparator achieves 143fJ...
This paper presents a successive approximation analog-to-digital converter (SAR ADC) achieving high power efficiency by adopting sub-range concept. Overlapping range greatly relieves the accuracy requirement on the first 6 bit resolving in coarse conversion. The error made in the coarse conversion is recovered during the rest 7 bit resolving in fine conversion. Hence, it significantly reduces the...
This paper presents a 6-bit, 1.2-GSample/s flash ADC for MB-OFDM UWB receivers fabricated in TSMC 0.13-mum CMOS 1P8M process. Using a dedicated track-and-hold amplifier (THA) at front, it can eliminate different paths skew between comparators and clock jitter degradation to the comparators. Moreover, the proposed converter is designed with averaging and interpolation technique so that the offset of...
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