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This paper presents a source synchronous receiver data lane design in 65nm CMOS process. The data lane circuit consists of a pre-amplifier which can compensate over 8dB channel loss and a half-rate digital CDR based on phase-interpolator. The CDR bandwidth is programmable by using a digital FIR filter. This design uses variable offset amplifier technology to increase sensitivity of the receiver. And...
In this paper, a novel clock and data recovery scheme for 10Gbps source synchronous receiver is presented in 65nm CMOS technology, which includes the implementation of a quadrature clock generation circuit and a 10Gbps CDR circuit. The quadrature clock generation circuit is based on an open loop delay line, avoiding the design of the complex DLL or PLL loop which is often used in source synchronous...
In this paper, a 10Gbps PI-based CDR circuit is presented in 65nm CMOS technology. The circuit is composed of a phase selector, a phase interpolator, a sample unit, a synchronize unit, a phase detector, and CDR logic. Half-rate clock is adopted to lessen the problems caused by high speed clocks and reduce power. The simulated worst phase step of phase interpolator is 26.7% larger than the average...
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