The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
With better spectral efficiency, multiple-input and multiple-output (MIMO) systems have drawn increasing attentions. Due to its near-optimal performance, K-best algorithm has been widely adopted for MIMO detection. To the best knowledge of the authors, this paper first proposes a joint detection and decoding (JDD) method for MIMO with low-density parity-check (LDPC) codes. By pruning the searching...
Single block-row quasi-cyclic low-density parity-check (QC-LDPC) codes are recently proposed. This kind of codes are favorable in applications because of their construction flexibility and good performance compared to PEG codes and array codes. However, the corresponding high row weight will increase the hardware complexity of the check node unit (CNU). In this paper, an area-efficient CNU architecture...
Low-density parity-check (LDPC) codes are one of the most promising error-correcting codes approaching Shannon capacity and have been adopted in many applications. However, the efficient implementation of high-throughput LDPC decoders adaptable for various channel conditions still remains challenging. In this paper, a low-complexity reconfigurable VLSI architecture for high-speed LDPC decoders is...
This paper presents an FPGA implementation for LDPC codes performance simulation. The goal is for fast evaluation of LDPC code to investigate the error floor. The hardware evaluation platform features by fast simulation speed and high precision. The construction of the platform is described. The critical modules designed in the platform such as LDPC encoder, decoder, and AWGN noise generator are presented...
In this paper, an efficient high-speed low-density parity-check (LDPC) decoder is presented. Single minimum decoding and non-uniform quantization schemes are explored to reduce the complexity of computation core and the memory requirement. Shifting structure is incorporated to significantly reduce the routing complexity of the LDPC decoder. The implementation of an 8192-bit LDPC decoder demonstrates...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.