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For the first time, nano-meter-scaled 1T-1R non-volatile memory (NVM) architecture comprising of RRAM cells built on vertical GAA nano-pillar transistors, either junction-less or junction-based, is systematically investigated. Transistors are fabricated using fully CMOS compatible technology and RRAM cells are stacked onto the tip of the nano-pillars (with a diameter down to ∼37nm) to achieve a compact...
This paper reports a 45 nm spin-transfer-torque (STT) MRAM embedded into a standard CMOS logic platform that employs low-power (LP) transistors and Cu/low-k BEOL. We believe that this is the first-ever demonstration of embedded STT MRAM that is fully compatible with the 45 nm logic technology. To ensure the switching margin, a novel "reverse-connection" 1T/1MT cell has been developed with...
For NiSi FUSI gate transistors, switching behaviors have been observed after breakdown (BD) under certain favorable conditions. The conductive BD path can be ??switched-off?? if a reverse bias, as opposed to the stressing voltage, is applied, a condition required for observing SET and RESET conduction in switching material systems. Using the percolation model of BD of gate dielectric systems, we explain...
How can a metal-oxide-semiconductor (MOS) transistor suffer from multiple dielectric breakdowns (BD) with severe structural damages (e.g., local melting and metal migration) remain functional? Our results show that the amorphization of Si in the vicinity of the BD forms an effective p-n diode which prevents terminal short from happening when reverse-biased.
Using scanning transmission electron microscope with high resolution electron energy loss spectroscopy, the chemical nature of the percolation path formed in ultrathin SiON layers is studied for digital and analog breakdown (BD). Our results show that the diameter of the percolation path dilates from 30 nm to 55 nm as the gate leakage current increases from 2 muA to 40 muA. Oxygen deficiency in the...
The prospect for the introduction of III-V semiconductors into the channel of n-type MOSFETs and thus replace Si with a high mobility material for 22 nm technology generation and beyond is examined in detail. The so-called implantfree (IF) III-V MOSFET architecture option is presented showing a fabricated n-type IF demonstrator suitable for scaling. We then focus on a prediction of the potential performance...
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