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In this work, ESD immunity enhancement for the HV n-channel LDMOS with source-end discrete islands fabricated by a TSMC 0.25 μm 60 V process was investigated. An nLDMOS device always has poor ESD capability. If discrete n+ islands are formed in the source end of an nLDMOS transistor, the It2 value of this DUT is upgraded by 4.92% as compared with that of the reference nLDMOS. Meanwhile, if an nLDMOS...
HV n-/p-LDMOS devices with the source-side extending into bulk-region to evaluate the electrostatic-discharge (ESD) protection robustness by a TSMC 0.25 µm 60 V process are investigated in this paper. After a systematic analysis, the trigger voltage (Vt1) values of the n-LDMOS with the source-side extending into the bulk-end either by uniformly or non-uniformly distributed manners that had decreased...
The pLDMOS related devices fabricated by a TSMC 0.25 µm 60 V process was investigated in this paper. For the ESD improvement, some DUTs inserting the N+ zone to form an embedded SCR in the drain end or guard-ring area, respectively. From the TLP testing results, the It2 values of the drain parasitic SCR npn-type and pnp-type could reach > 7 A, higher than that of the traditional pLDMOS device....
The impacts of current-path variation on the ESD robustness of nLDMOS devices as the drain-side modulation by a 0.18 μm/40 V process are evaluated in this paper. From the transmission-line-pulsing (TLP) measurement, the secondary breakdown current (It2) of an nLDMOS with the drain-side embedded SCR structure & "pnp" arrangement (DUT-2) increased from 2.498 A up to > 7 A (at least...
A novel robust sliding-mode controller using neural networks (NNs) is given for trajectory tracking control of permanent magnet spherical actuator (PMSA) with external disturbance and system model errors. The controller is established including sliding-mode scheme and the neural networks. The radial basis function (RBF) neural networks are chosen to approximate the unknown model and uncertainty, as...
In this paper, Electrostatic-Discharge (ESD) reliability study of 45-V HV pLDMOS devices with the source-side discrete islands is investigated. A pure pLDMOS transistor is always frail in ESD harms (It2= 0.107-A). However, if a pLDMOS device with two embedded SCRs (drain side npn-arranged); the corresponding It2 current can be upgraded to 0.644-A. Furthermore, as a pLDMOS-SCR (npn-arranged stripe...
N-channel MOSFETs are often applied to the input/output ports as electrostatic discharge (ESD) protection elements, usually in the form of multi-finger placement. However, the non-uniform turned-on situation always occurred, therefore these sub-nMOSFETs can't conduct-on simultaneously. The ESD current will be passed through a few turned-on MOSFETs. It was due to the RBulk resistance of parasitic bipolar...
For the reliability considerations, a 60-V power p-channel LDMOS transistor co-designed with none-OD zone in the bulk end by a 0.25-μm process will be evaluated in this paper. From the experimental data found that as the none-OD zones inserting, meanwhile the none-OD zone percentage was increased, the anti-ESD capability will be strengthened too, i.e. its It2 value is improved by using this manner...
In order to effectively improve the ESD capability of a p-channel lateral-diffused MOS device, we aimed at the anti-ESD protection capability of the different layout types in the drain-side for the 0.25-μm 60-V high voltage p-channel LDMOS devices. Here, a drain-side pnp arranged-type in a pLDMOS-SCR parasitic structure is used to investigate the layout placement effect. At first, the layout type...
The impact of layout-type dependences on anti-ESD robustness in a 0.25 μm 60 V process will be investigated in this paper, which included the traditional striped-type nLDMOS, waffle-type nLDMOS, and nLDMOS embedded with a pnp-manner SCR devices. Then, these nLDMOS devices are used to evaluate the influence of layout architecture on trigger voltage (Vt1), holding voltage (Vh) and secondary breakdown...
How to effectively enhance the reliability robustness in high-voltage BCD processes is an important issue. A p-channel lateral-diffused MOSFET with an embedded SCR which is formed by implanting N+ doses in the drain side and divided into five regions, this structure called as the "pnpnp" arranged-type of pLDMOS-SCR in this paper (diffusion regions of the drain side is P+-N+-P+-N+-P+). Then,...
An LDMOS (lateral-diffused MOS) is often used to as the ESD device in a high-voltage circuit for its low on-resistance benefit. But, it has several serious disadvantages, including the Vh value is not high enough and the device in a multi-finger structure can't completely turn on which resulting in the ESD capability per unit length is very low. So, the non-uniform turned-on phenomenon is seriously...
Stars in a star map can be regarded as a point pattern, and we can utilize the matching of point pattern to recognize the star pattern. First, the nth Radius-Weighted-Mean Points (RWMPs) are proposed which are invariant to translation, rotation and scaling, and then, a RWMP-based feature vector is constructed which is still invariant to translation and rotation. The candidate referenced star images...
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