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This paper describes the design of a low power multi-standard transceiver in 28nm CMOS technology. Using novel circuit techniques and implementation features, the transceiver can operate at data rates of 1.2–6.8Gb/s while supporting a wide range of communication standards, including SGMII, QSGMII, PCIE, SATA, USB3, XAUI and RXAUI. Power consumption per lane is 23mW at 0.9V for SATA3 at 6Gb/s, with...
A quad-channel, 112–128 Gb/s coherent DP-QPSK transmitter in 40 nm CMOS is presented. The 27.9–32.1 Gb/s TX features a half-rate architecture with a 2-tap FIR. The measured output has an amplitude of 1.2Vpp-diff with 1.3 ps deterministic jitter (DJ). The DP-QPSK TX's precoded data alignment is maintained through the quad-lane transmitter by the use of an automatic synchronous feedback loop, removing...
This paper presents a wide-band analog Fractional-N clock synthesizer operating from 8 to 12.4GHz suited for data communication standards. The synthesizer generates a low noise clock with rms jitter of 288–460fs, yet maintains wide loop bandwidth from 1.5 to 4.3MHz. The design consumes 16.9mW from a 1V supply, while occupying an area of 0.39mm2 in a 40nm CMOS technology.
Recently developed 40Gb/s optical modulation formats such as return-to-zero differential quadrature phase-shift keying (RZ-DQPSK) and carrier-suppressed return-to-zero differential quadrature phase-shift keying (CS-RZ-DQPSK) are promising, since they offer high optical signal-to-noise ratio, high transmission efficiency and can tolerate large chromatic dispersion [1, 2]. The recent advances in processing...
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