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The ∼20% Id,sat improvement is demonstrated successfully on the Si and Ge n-FinFETs with the implement of D-SMT stressor for the first time, based on the optimization of dislocation angle and the understanding of crystal re-growth velocities along different surface planes and directions in Si and Ge. The mobility enhancement ratio with D-SMT stressor in Ge n-FinFET (37%) is found to be larger than...
Bias Temperature Instability (BTI) degradation and recovery with different types of MOL capping layers are investigated in a 20nm Replacement Metal Gate (RMG) CMOS technology. It is found that less compressive RMG capping layers substantially improve reliability and device performance because of less hydrogen within the RMG capping material. The hydrogen content plays an important role in BTI degradation...
Three bits per cell NAND Flash Memory Technology for 30 nm and beyond has been successfully developed with floating gate technology. Tight natural Vth distribution, wide program/erase window, and good cell reliability such as program disturb, endurance and data retention are obtained. 8 level Vth distributions are successfully demonstrated.
A floating gate NAND flash memory technology for 30 nm and beyond has been successfully developed. Wide program/erase window, tight natural threshold voltage (Vth) distribution, and good cell reliabilities such as program disturb, program/erase endurance and data retention are successfully demonstrated, which are essential to realize super MLC.
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