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Graphene based field effect transistors (GFETs) are quite sensitive to surface effects, such as the influence from surface adsorbents. In this work, it demonstrates the meta/ferroelectric [P(VDF-TrFE)]/graphene(MFG) configuration can realize the novel nonvolatile memories where competition between the ferroelectric polarization and charging / discharging of graphene / interface traps has been addressed.
In this work, we apply nano-embossing technology to fabricate Pb(Zr0.3, Ti0.7)O3 (PZT) ferroelectric thin film nanostructures and investigate the influence of the patterning process on the material and ferroelectric properties by using SEM, XRD and Precision Ferroelectric Tester. Embossing process has been optimized for embossing depth and pattern profile. It was found that embossing will result in...
Although the strained-Si channel engineering seems to be rather compatible with the existing mainstream CMOS process, the use of strained Si on SOI virtual substrates introduces new process and integration issues that need to be addressed for successful manufacturability and reliability. Even for ideal strained Si on SOI substrates, the impacts of various CMOS process steps, e.g., patterning, oxidation,...
An experimental study on Schottky-barrier height (SBH) tuning using ion implantation followed by drive-in anneal of As, B, In, and P in preformed NiSi and PtSi films is presented. Measured on B-implanted NiSi and PtSi Schottky diodes, the effective SBH on n-type Si is altered to ~1.0 eV. For As- and P-implanted diodes, the SBH on p-type Si can be tuned to around 0.9 eV. The process window for the...
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