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Here we consider one special situation for approximate computing. Given a specification, S, in a truth table and its corresponding multi-level logic circuit implementation, I, S is changed to S' by only changing the truth table value for exactly one minterm from 0 to 1 or 1 to 0. We would like to transform I into I' in such a way that I' is equivalent to S' This is a sort of basic operations for approximate...
Trace buffers play a crucial role in curbing the obstacle of limited observability of internal states for error localization during post-silicon stage. Given the constraint of area over-head, selecting appropriate signals which are to be stored in the trace buffers is of paramount importance for the overall success of this observability enhancement mechanism. This paper proposes a register-transfer...
Previous works have shown that given an initial set of test patterns for single faults, relatively few additional tests are required to cover all multiple faults. In this paper, the exact situations in which the test patterns for single stuck-at faults do not detect multiple stuck-at faults are examined. We present proofs which show the conditions that is required to be met for ATPG on single faults...
We show a way to extract inductive-invariant from sequential circuits by analyzing only one time frame. The extraction problem is formulated with Quantified Boolean Formula which says if some relation is satisfied on the inputs coming from subsets of flipflops, the same relation must be satisfied on the outputs going to those flipflops. The QBF problem can be solved by repeatedly applying SAT solvers,...
In this paper, we introduce a formal and scalable debugging approach to derive a reduced ordered set of design error candidates in polynomial datapath designs. To make our debugging method scalable for large designs, we utilize a Modular Horner Expansion Diagram (M-HED), which has been shown to be a scalable high level decision model. In our method, we extract data dependency graphs from the polynomial...
Early generation of effective high level test patterns can significantly reduce Automatic Test Pattern Generation (ATPG) efforts in gate level. This paper proposes an ATPG methodology targeting non-scan designs. Although our methodology checks all execution paths, a decision procedure is applied to detect the false paths very early and split the cases before generating high level test patterns. Experimental...
This paper proposes a non-scan gate-level Automatic Test Pattern Generation (ATPG) methodology which keeps the regularity in the arithmetic operations while reasoning about these operations for generating high-level test patterns from only faulty behavior of the design. Then by considering generated high-level test patterns as constraints and passing them to a SMT-solver we are able to automatically...
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