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This paper proposes a fast full-chip synthesis methodology which can be built a custom Network-on-Chip (NoC) topology for NoC-based systems. The processors and their communications are synthesized simultaneously in the system-level floorplanning process. The proposed method leads to accurate area estimation, which makes an algorithm much more efficient than previous approaches. Moreover, the wirelength-aware...
This paper presents an embedded debugging/performance monitoring engine (EDPME), which is capable of collect run time characteristics, detect AHB on-chip bus protocol error/inefficiency, and capture on-chip AHB bus traces at various abstraction levels with compression ratio up to 98% for a low cost tile-based 3D graphics SoC development.
This paper proposes an efficient HW/SW integrated verification methodology for 3D Graphics (3DG) acceleration on SoC development. The proposed methodology is built for verifying 3DG SoC with FPGA emulation and contains a GUI analyzing tool for displaying emulation results and assisting HW/SW debugging automatically. With the verification methodology, designers can detect unobvious bugs from HW and...
This paper presents an 8.69 Mvertices/s, 278 Mpixels/s, 15.7 mm2 tiled-based 3D graphics SoC HW/SW supporting OpenGL ES 1.0 running at 139 MHz. The SoC also includes embedded circuitry to monitor run time characteristics, detect bus protocol error/inefficiency, and capture bus traces at various abstraction levels with compression ratio up to 98%.
Portable mobile computing and communication applications demand low-power and low-energy with high performance. These competing demands drive SoC development. Especially, 3D graphics-intensive applications are predicted to become widely available on a variety of portable mobile devices ranging from laptops to PDAs to mobile phones. Such 3D graphics coprocessors were originally developed for home computers...
The nanoscale technology makes the design concept of the sea of processors possible in the coming billion transistor era for high performance implementations. In order to solve the scalability, complexity and timing problem of the communication between these processors in a large scale SoC (System on a Chip) implementation, the NoC (Network on a Chip) or OCN (On-Chip Network) paradigm, a replacement...
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